USB 3.0 ARCHITECTURE

USB 3.0 ARCHITECTURE:

Physical Layer:

        The physical layer defines the PHY portion of a port and physical connection between the Host and Device.

The physical connection consist of two differencial data pairs with signalling rate 5Gbps.

In electrical aspects the path are characterised as a Transmitter,Channel and Receiver.

In electrical level each differencial link is initialised by enablink its receiver termination.

The transmitter is responsible for detecting the far end device information as an indication of a bus connection and informing the link layer so the connect status can be factored into link operation and management.

USB 3.0 cables have separate shielded differential pairs of lines for transmitting and receiving data. These lines exist along with the USB 2.0 signals.

Thus, a USB 3.0 cable contains a total of 9 pins, including the 4 pins which are part of USB 2.0 cable. The maximum length of a USB 3.0 cable is limited to 3 meters due to the high signaling rate that it supports.

As for the power distribution by the USB 3.0 host, 150mA is considered as the unit load. The USB 3.0 host supplies 1 unit load of current for unconfigured devices and 6 unit loads of current for configured devices.

The USB 3.0 host detects the device connection based on the receiver end termination, and the transmitter is responsible for doing this action. USB 3.0 uses spread spectrum clocking on its signaling.

Spread spectrum clocking spreads the energy of the signal over a larger frequency band rather than concentrating it over a small frequency band at a high level. This helps to reduce EMI emissions.

The USB 3.0 physical layer supports Low Frequency Periodic Signaling (LFPS) which is used to manage signal initiation and low power management on the bus to consume less power on an idle link.


Link layer:

The link layer is responsible for maintaining a reliable and robust communication channel between the host and device. The Link Training and Status State Machine (LTSSM) is the core of the USB 3.0 link layer and defines link connectivity and link power management states and transitions.

 LTSSM consists of 12 states:

 Four link power states for better power management:
       
    U0 – normal operational mode
       
    U1 – Link idle with fast exit (PLL remains on)
       
    U2 – Link idle with slow exit (PLL may be off)
       
    U3 – Suspend
       
    U1, U2, U3 have increasingly longer wakeup times than U0, and thus allow transmitters to go into increasingly deeper sleep.
   
    Four link initialization and training states (Rx.Detect, Polling, Recovery, Hot Reset).
   
    Two link test states (Loopback and Compliance Mode).
   
    SS.Inactive (link error state where USB 3.0 is non-operable).

        SS.Disabled (SuperSpeed bus is disabled and operates as USB 2.0 only).

Link commands are used to maintain the link flow control and to initiate the change in link power state.


Protocol layer:

The protocol layer defines the communication rules between a host and device. USB 2.0 transactions consist of 3 packets: token, data, and handshake.

A transaction is initiated with the token packet and this is always from the host. Data packets deliver the payload data and can be sourced by the host or device. Handshake packets acknowledge the error-free receipt of data and are sent by the receiver of data.

In the case of SuperSpeed, however, to save bandwidth the token is incorporated into the data packet for OUT transactions. The token is replaced by the handshake for IN transactions; i.e., an ACK packet acknowledges the previous data packet that has been sent and requests the next data packet.

USB 3.0 packets are routed to the specific device with the help of the route string in the packet header. USB 3.0 does not poll for the readiness of the devices. If a device responds with “NRDY” (Not Ready) to an IN Transaction Packet (TP) from the host, then the host stops talking to that device until the device sends the “ERDY” (ready) packet saying that now it is ready to transmit the data.

USB 3.0 supports transmitting data in bursts (multiple data packets) without receiving an acknowledgement. The protocol allows efficient bus utilization by concurrently transmitting and receiving over the bus. A transmitter (host or device) can burst multiple packets of data back-to-back while the receiver can transmit data acknowledgements without interrupting the burst of data packets.

Also, the host may simultaneously schedule multiple OUT bursts to be active at the same time as IN bursts.

USB 3.0 has enhanced the bulk capabilities of USB 2.0 by adding a protocol called “Stream”. This allows you to accept multiple commands on a pipe from the host, and allows you to complete them out of order using the stream IDs.